1. Field of the Invention
The present invention relates generally to a fluorescent lamp ballast and, more particularly, to circuitry for providing transient prevention for use with a dimmable cold cathode fluorescent lamp (CCFL) ballast.
2. Description of the Related Art
Open circuit protection is often required in electronic ballasts for safety and reliability reasons. When the lamps, i.e., loads, are not connected to the ballast outputs, there will be a very large undesirable voltage occurring across the ballast outputs if protection is not in place. This unloaded case can result in an output voltage which may be on the order of 5xc3x97 higher than a nominal output with the lamps connected (e.g., 3500 volts instead of 700 volts). The overvoltage condition can damage ballast components and/or cause the ballast running into an unexpected state, and thus eventually damaging the ballast.
Overvoltage protection is required in lamp driving circuits as described in U.S. Pat. Nos. 5,680,017, 6,011,360 and 6,084,361; the contents of each of which are hereby incorporated herein by reference.
FIG. 1 illustrates a block diagram of the liquid crystal display (LCD) backlight inverter in accordance with the prior art, designated generally by reference numeral 100. The LCD backlight inverter 100 typically comprises a power stage module 6 for operating a lamp(s), such as L18 and L210. Lamps 8 and 10 may be, but are not limited to illuminating a liquid crystal display (LCD) of a desktop computer (not shown). The LCD backlight Inverter 100 further comprises a startup logic module 16, a short/open protection module 15, and a control IC (integrated circuit) 20. It is noted that a pulse width modulating module may be incorporated in the configuration of FIG. 1 with minor modifications to control signals between the IC 20 and the power stage module 6.
IC 20 performs a number of functions including: regulating lamp power by sensing lamp current and voltage, receiving and outputting control and non-control signals, generating an internal oscillation for driving power switches (not shown) included as part of the power stage module.
FIG. 1 shows two control signals G1 and G2 which represent output control signals for driving half bridge switches internal to the power stage module 6, which regulates the output power of transformers internal to power stage module 6 to drive L1 and L2. The startup logic module 16 powers the IC 20 (See signal Chip_Vdd) under normal operating conditions and prevents IC 20 from receiving power under fault conditions or whenever an xe2x80x9cenablexe2x80x9d signal to the startup logic module 16 is not activated. At startup, signal Chip_Vdd will ramp up to reach a threshold voltage, Vdon. The IC 20 is said to be in an oscillation mode after the threshold voltage Vdon is reached. The startup logic module 16 is further used to disable IC 20 to prevent detected overvoltages from damaging IC 20, as described further below.
FIG. 2 is an illustration depicting particular elements of FIG. 1 and additionally provides a detailed circuit diagram of the power stage module 6 of FIG. 1. The power stage module 6 is based on a voltage-fed, half-bridge resonant converter for providing a high starting voltage (e.g.,  greater than 1700 Vrms) to ignite the lamps and a current source drive to run the lamps in the on-state with high efficiency (i.e.,  greater than 85%). As shown in FIG. 2, power stage module 6 comprises two power switches, M131 and M232. In the present embodiment, M131 is a high side power MOSFET switch and M232 is a low side power MOSFET switch. The power switches may also be embodied as insulated gate bipolar transistors (IGBTs) in alternate embodiments. The half bridge switches M1 and M2 are each driven in a steady state mode of operation, with non-overlapping gate signals, G1 and G2, respectively. As shown, the power switches are arranged in a half bridge topology, having a common point 33 for sourcing an L-L-C resonant circuit comprising inductor T337, transformers T136, T238, and capacitor C39 and C40. Lamp L18 is shown connected to a secondary winding of transformer T136 and lamp L210 is connected to a secondary winding of transformer T238 without ballasting capacitors. In the exemplary embodiment, lamps L18 and L210 are cold cathode fluorescent lamps (CCFL). It is well known to those in the art that other types of loads may be substituted for the lamps L18 and L210 in different applications. By not using ballasting capacitors, the reactive power handled by the output transformers is minimized. The two lamps L18, L210 share a common ground and a common lamp current sensing resistor RSENSE.
Power switch M232 is driven to conduct alternately by a control signal G246 provided by IC 20, and power switch M131 is driven to conduct alternately by a control signal G148 provided by IC 20. Lamp power regulation is provided by closed-loop feedback control. A Lamp voltage is obtained from a tightly coupled winding on the secondary of output transformers T136 and T238, while the lamp current is detected across resistor RSENSE tied in series with the lamp. The lamp current detected across RSENSE is provided as an input to pins LI1 and LI2 of IC 20 to represent the average current in the lamp. The IC 20 then drives the half bridge frequency in a direction to achieve the desired lamp power as dictated by a reference input to the controller. In this case, the reference input is the DIM input pin to the controller.
With continued reference to FIG. 2, the startup sequence of the liquid crystal display backlight inverter of the prior art will be described to illustrate the limitations of the prior art regarding the inability to protect against the occurrence of a startup overvoltage transient.
Initially, (i.e., during startup) power switches M131 and M232 are in a nonconducting state. Input signal Chip_Vdd 43 is off as a consequence of ENABLE 42 being off. Inverter 100 input Vdd 44 is applied to the circuit and consequently a node voltage VNODE 40 at a common point between C340 and C141 will be charged to Vdd/2 as a consequence of C340 and C141 having the same capacitance value. At the point in time when the ENABLE signal 42 is switched on, IC 20 supply Chip_Vdd 43, which is sourced from supply voltage Vdd 44, slowly charges from zero volts and is applied to the pin of IC 20 labeled Vdd. IC 20 supply Chip_Vdd 43 slowly charges to reach a threshold voltage Vdon. Prior to reaching the threshold level, Vdon, in response, IC 20 will activate pin G2 to cause output signal G2 to maintain M232 in an ON state, and high side power switch M131 in an OFF state.
As previously stated, IC 20 does not oscillate prior to Chip_Vdd reaching a threshold level Vdon. Prior to IC supply Chip_Vdd 43 reaching the threshold level Vdon, M232 is maintained in an ON state thereby creating a path through T2, T1, T3 and M2, thereby allowing node VNODE 40 to discharge to zero. This creates a DC offset (asymmetry) in sensing inductor T337 which is converted to an unbalanced sensing signal along line 54. The voltage asymmetry is sensed by input inductor current sensing pin RIND of IC 20 which drives the half bridge frequency undesirably lower towards the resonant frequency. In particular, signals G2 and G1 begin to prematurely oscillate at an undesirable low frequency thus driving the low and high side power switches M232 and M131, respectively, at the undesirable low frequency rate. The low switching rate is undesirable in that it is near the resonant frequency of the L-L-C resonant circuit formed by resonant inductor T3, transformers T136, T238, and capacitors C39 and C40, thereby causing the startup voltage transient.
The undesirable low frequency rate at which power switches M131 and M232 are driven is a consequence of the controller being an on-time controller type as opposed to a frequency controller. On-time controllers are described in detail in U.S. Pat. No. 6,084,361. On-time controllers characteristically control the switching frequency by indirect means. Specifically, frequency control is performed in response to sensing an external inductor""s zero crossings. By contrast, frequency controllers do not rely upon an external sensing signal to perform frequency control and are therefore less immune to overvoltage transients.
FIG. 3 is a waveform diagram illustrating the process described above. As shown, channel 1 represents IC supply Chip_Vdd 43 which is sourced from voltage Vdd 44. IC 20 maintains the M232 gate in an ON state prior to Chip_Vdd 43 reaching a predetermined threshold voltage, Vdon. It is this time 49 (i.e., the time prior to Chip_Vdd reaching a threshold level Vdon) associated with Chip_Vdd that results in the M2 gate operating at an undesirable low frequency as illustrated by xe2x80x9cAxe2x80x9d (See channel 4). Channel 2 represents the VNODE 40 voltage shown initially discharged to zero volts due to the path to ground created through M232 during start-up, i.e., prior to Vdon being attained. Consequently, VNODE 40 increases from zero which creates the inductor current asymmetry in T337 as discussed above. Channel 3 illustrates the inductor current asymmetry sensed by the RIND input of IC 20 as a result (note the asymmetric spikes towards the left side of the waveform). Channel 4 illustrates the effect of the detected asymmetry. Specifically, switch M232, which is shown to be initially driven at an undesirably low switching rate or frequency, near the frequency of the L-L-C series resonant circuit causing an startup overvoltage transient (See interval A). It is noted that this transient persists for an extended time (e.g., 400 xcexcs) because capacitors C141 and C340 are relatively large (e.g., 100 xcexcf each) and therefore node VNODE 40 takes a relatively long transient time to stabilize at Vdd/2 (See Point B). During this time, the low switching rate of gate M232 persists until VNODE 40 re-stabilizes back to Vdd/2.
Another undesirable consequence of the prior art configuration is that due to the long transient, the inverter may not be able to startup.
Accordingly, it is desirable to provide a liquid crystal display backlight inverter which operates the lamp under more stable startup conditions. The overvoltage prevention circuitry should particularly address the relatively long transient time required for the inductor current waveform to become symmetric again.
The present invention provides an improved liquid crystal display (LCD) backlight inverter which overcomes the problems associated with the prior art. More particularly, the present invention provides a circuit for preventing a startup transient (i.e., overvoltage condition) in a LCD backlight inverter.
In a first embodiment according to the present disclosure, there is provided an improved LCD backlight inverter comprising: a power stage that includes a first power switch and a second power switch that powers one or more loads (e.g., lamps); a controller that generates control signals, that receives an IC supply equaling or exceeding a prescribed threshold level, and provides a steady-state internal oscillation that drives said first and second power switches; and a transient prevention circuit that maintains said second power switch in a nonconducting state until at least a time at which said IC supply reaches said prescribed voltage threshold.
In a second embodiment according to the present disclosure, there is provided an improved LCD backlight inverter comprising: a power stage that includes a first power switch and a second power switch that powers one or more loads (e.g., lamps); a controller that generates control signals, that receives an IC supply input signal having a voltage level corresponding to a voltage level of said voltage source, and that generates and outputs a signal corresponding to an internally generated oscillation that drives said first and second power switches; and an transient prevention circuit that prevents said oscillator from generating said internally generated oscillation until at least a time at which said IC supply input signal reaches a prescribed threshold value.